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| NEC's LOW POWER GPS RF RECEIVER BIPOLAR ANALOG + INTEGRATED CIRCUIT UPB1009K DESCRIPTION The PB1009K is a silicon monolithic IC developed for GPS receivers. This IC integrates a full VCO, second IF filter, 4-bit ADC, and digital control interface to reduce cost and mounting space. In addition, its power consumption is low. Moreover, use of a TCXO with frequency of 16.368 MHz/16.384 MHz, 14.4 MHz, 19.2 MHz, or 26 MHz switchable with an on-chip divider is possible. NEC's stringent quality assurance and test procedures ensure the highest reliability and performance. FEATURES * Double conversion * Multiple system clocks * A/D converter * High-density RF block * Supply voltage * Low current consumption * High-density surface mountable : fREFin = 16.368 MHz, f1stIFin = 61.380 MHz, f2ndIFin = 4.092 MHz : fREFin = 14.4, 16.384, 19.2, 26 MHz, f1stIFin = 62.980 MHz, f2ndIFin = 2.556 MHz : On-chip switchable frequency divider (1/N = 100, 3/256, 9/1024, 65/4096) : On-chip 4-bit A/D converter : On-chip VCO tank circuit and 2ndIF filter : VCC = 2.7 to 3.3 V : ICC = 26.0 mA TYP. @ VCC = 3.0 V, N = 100 : 44-pin plastic QFN APPLICATIONS * Consumer use GPS receiver of reference frequency 16.368 MHz, 2nd IF frequency 4.092 MHz * Consumer use GPS receiver of reference frequency 14.4, 16.384, 19.2, 26 MHz, 2ndIF frequency 2.556 MHz Caution Observe precautions when handling because these devices are sensitive to electrostatic discharge. UPB1009K ORDERING INFORMATION Part Number Package 44-pin plastic QFN Supplying Form * 12 mm wide embossed taping * Pin 1 indicates pull-out direction of tape * Qty 1.5 kpcs/reel, Dry pack specification PB1009K-E1 Remark To order evaluation samples, contact your nearby sales office. Part number for sample order: PB1009K 2 UPB1009K PRODUCT LINE-UP (TA = +25C, VCC = 3.0 V) Type Part Number Functions (Frequency unit: MHz) Pre-amplifier + RF/IF downconverter + PLL synthesizer REF = 16.368 1stIF = 61.380/2ndIF = 4.092 REF = 14.4, 16.384, 19.2, 26 1stIF = 62.980/2ndIF = 2.556 On-chip 4-bit ADC VCC (V) 2.7 to 3.3 ICC (mA) 26.0 CG (dB) Package Status Clock PB1009K Frequency Specific 1 chip IC 44-pin plastic QFN New Device PB1008K 2.7 to 3.3 LNA + Pre-amplifier + RF/IF down-converter + PLL synthesizer REF = 27.456 1stIF = 175.164/2ndIF = 0.132 On-chip 2-bit ADC Pre-amplifier + RF/IF downconverter + PLL synthesizer REF = 16.368 1stIF = 61.380/2ndIF = 4.092 REF = 16.368 1stIF = 61.380/2ndIF = 4.092 2.7 to 3.3 18.0 100 to 120 36-pin plastic QFN PB1007K 25.0 100 to 120 36-pin plastic QFN Available PB1005K 36-pin plastic QFN Remark Typical performance. Please refer to ELECTRICAL CHARACTERISTICS in detail. SYSTEM APPLICATION EXAMPLE GPS receiver RF block diagram PD1 and PD2 in the figure are Power Save Mode control pins. MS1 and MS2 in the figure are TXCO (GPS, W-CDMA, PDC, GSM) control pins. 1stIF = 61.38 MHz 62.98 MHz IF SAW RF = 1575.42 MHz 1stLo = 1636.8 MHz 1638.4 MHz Pre- 1st. amp mix 2ndIF = 4.092 MHz 2.556 MHz IF Amp - + + - DC trim RF LNA SAW 2nd MIX RF AGC LPF IF /25 4bit ADC Para Data Regulator PD1 /N Tank Cont. PLL - + Samp Clk AGC cont PD2 MS1 MS2 TCXO Caution This diagram schematically shows only the PB1009K's internal functions on the system. This diagram does not present the actual application circuits. GPS baseband 3 UPB1009K PIN CONNECTION AND INTERNAL BLOCK DIAGRAM GNDsub AGCout VDDbuf AGCin SCKin GNDbuf 23 22 GNDana - - D3 D2 D1 33 VDDlogi 34 GNDlogi 35 PD1 36 PD2 37 1stIFin 38 IFVCC 39 32 31 30 29 28 27 D0 26 25 24 VDDana + + 4bit ADC + - 21 DCOFFin 20 DCOFFout 19 2ndIFin Pwdctrl Logic VGC LPF IFamp 1/4 18 2ndIFout 17 IFGND 1st IFout 41 LNAVCC 42 LNAGND 43 PreAmp LNAin 44 1 2 3 4 1stMIX 65/1024 9/256 1stMIXVCC 40 16 CLKout 15 PLLGND PLL PD Fref 14 PLLVCC 1/25 3/64 OSC CP 5 6 7 8 9 10 11 13 Refin 12 MS2 1stMIXin LOVCC VCO1 LNAout RegGND GND (1st-MIX) Rext MS1 VCO2 LOGND 4 CPout UPB1009K PIN EXPLANATION Pin No. 1 2 Pin Name Function and Application Internal Equivalent Circuit PreAMPout Rext Output pin of preamplifier. Connect a resistor for the reference constant-current power supply to this pin. Ground this pin at 22 k. Ground pin for regulator. Power supply voltage pin for preamplifier. Connect a bypass capacitor to this pin to reduce the high-frequency impedance. Ground pin of preamplifier. Input pin of preamplifier. 1 42 3 42 RegGND PreAmpVCC Regulator 44 2 43 44 PreAmpGND PreAmpin 43 3 4 5 40 1stMIXin 1stMIXGND 1stMIXVCC 1stMIX input pin. Ground pin for first MIX. Power supply voltage pin for RF mixer. Connect a bypass capacitor to this pin to reduce the high-frequency impedance. Output pin of RF mixer. Insert an IFSAW filter between this pin and pin 37. The VCO oscillation signal can be monitored on this pin. 40 Gibert Cell 4 41 41 1stIFout Bias 5 5 UPB1009K Pin No. 6 12 Pin Name Function and Application Internal Equivalent Circuit High : VCC - 0.3 to VCC (V) MS1 : L TCXO : 19.2 MHz MS2 : H MS1 : H TCXO : 14.4 MHz MS2 : L MS1 : H TCXO : 26 MHz MS2 : H 12 6 11 CPout Output pin of charge pump. Connect external R and C to this pin to set a dumping factor and natural angular frequency (Isink = Isource = 0.45 mA). 14 15 13 Refin Reference frequency input pin. Connect an external reference transmitter (such as TCXO) to this pin. 11 14 PLLVCC Power supply voltage pin of PLL. Connect a bypass capacitor to this pin to reduce the high-frequency impedance. 15 15 PLLGND Ground pin of PLL. 14 16 CLKout Clock (fTCXO) output pin (IC test pin). from divider Sink Bias Source Bias Bias MS1 MS2 Low : 0 to 0.3 (V) MS1 : L MS2 : L TCXO : 16.368, 16.384 MHz 14 16 15 6 UPB1009K Pin No. 7 Pin Name Function and Application Internal Equivalent Circuit LoVCC Power supply voltage pin of VCO. Connect a bypass capacitor to this pin to reduce the high-frequency impedance. 7 VCO out VCO cont 9 10 LoGND Ground pin of VCO. 10 17 IFGND Ground pin of IF block. 39 18 2ndIFout Output pin of IF amplifier. 38 1stIFin Input pin of second IF mixer. 38 18 Bias 39 IFVCC Power supply voltage pin of IF block. 17 To divider 8 9 VCO1 VCO2 IC test pin. Leave this pin open when the PB1009K is mounted on board. 8 7 UPB1009K Pin No. 19 Pin Name Function and Application Internal Equivalent Circuit 2ndIFin Input pin of ADC buffer amplifier. 24 20 DCOFFout Output pin of DC trimming OP amplifier. 4.7 k 21 DCOFFin 22 22 23 GNDana GNDbuf Ground pin for OP amplifier and ADC power supply. 24 24 VDDana Power supply pin for OP amplifier and ADC comparator. 31 25 VDDbuf Power supply pin for output driver amplifier of ADC. Connect this pin to the ground pin of the A/D converter via a bypass capacitor to reduce the high-frequency impedance. PB 22 25 26 GNDsub Ground pin of CMOS substrate. A Y inv 27 29 28 30 27 28 29 30 31 D0 D1 D2 D3 SCKin Digital signal output pins. LSB = D0, MSB = D3 Sampling clock signal input pin. 23 24 32 AGCin AGC control pulse signal input pin. 33 AGCout AGC control signal output pin. Bias 21 32 22 8 6.8 k 20 33 DC trimming pulse input pin. Connect this pin to pin 20 via a capacitor to convert an input pulse signal into DC. 19 1.8 k 6.8 k UPB1009K Pin No. 34 Pin Name Function and Application Internal Equivalent Circuit VDDlogi Power supply voltage pin for power control logic. Ground pin for power control logic. Low : 0 to 0.3 (V) High : VCC - 0.3 to VCC (V) PD1 : L PD2 : L Sleep mode (all circuits off). 34 35 36 37 GNDlogi PD1 PD2 36 37 PD1 : L Warm-up mode PD2 : H (PLL on). PD1 : H Calibration mode PD2 : L (PLL + IF + ADC on). PD1 : H Active mode PD2 : H (all circuits on). 35 9 UPB1009K ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Total Circuit Current Power Dissipation Operating Ambient Temperature Storage Temperature Symbol VCC ICCTotal PD TA Tstg Test Conditions TA = +25C TA = +25C TA = +25C Note Ratings 3.6 100 266 -40 to +85 -55 to +125 Unit V mA mW C C Note Mounted on double-sided copper-clad 50 x 50 x 1.6 mm epoxy glass PWB RECOMMENDED OPERATING RANGE Parameter Supply Voltage Operating Ambient Temperature RF Input Frequency 1st LO Oscillating Frequency 1st IF Input Frequency 2nd LO Input Frequency 2nd IF Input Frequency Reference Input/Output Frequency Symbol VCC TA fRFin f1stLOin f1stIFin f2ndLOin f2ndIFin fREFin fREFout VIL1 MIN. 2.7 -30 - - - - - - 0 VCC - 0.3 0 VCC - 0.3 TYP. 3.0 +25 1 575.42 1 636.8/1 638.4 61.38/62.98 65.472/65.536 4.092/2.556 TCXO - - - - MAX. 3.3 +85 - - - - - - 0.3 Unit V C MHz MHz MHz MHz MHz MHz Clock mode control voltage (Low Level) Clock mode control voltage (High Level) Power-down control voltage (Low Level) Power-down control voltage (High Level) V VIH1 VCC V VIL2 0.3 V VIH2 VCC V 10 UPB1009K POWER-DOWN CONTROL MODE The PB1009K consists of an RF block, an IF block, and a PLL block. By controlling reduction of power to each block (by applying a voltage to the PD1 and PD2 pins), the following four modes can be used. Mode No. 1 2 3 4 Mode Name Test Conditions PD1 Active mode Calibration mode Warm-up mode Sleep mode L H H L PD2 H H L L ON OFF OFF OFF RF Block IF Block (IF + ADC) ON ON OFF OFF PLL Block ON ON ON OFF Caution To use only the active mode and sleep mode, fix PD1 to L and select the desired mode with PD2. REFERENCE CLOCK CONTROL MODE The divided frequency can be selected as follows so that it can be shared with the TCXO of each system. TCXO Frequency Test Conditions PD1 16.368 MHz (GPS) 16.384 MHz (GPS) 19.2 MHz (W-CDMA) 14.4 MHz (PDC) 26 MHz (GSM) L PD2 L 1/100 16.368 MHz 16.384 MHz 19.2 MHz 14.4 MHz 26 MHz 1/N Phase Comparison Frequency L H H H L H 3/256 9/1024 65/4096 Caution When the reference clock frequency is 16.368 MHz, the 1stIF frequency and 2ndIF frequency are 61.38 MHz and 4.092 MHz, respectively. They are respectively 62.98 MHz and 2.556 MHz in all other cases. 11 UPB1009K ELECTRICAL CHARACTERISTICS (TA = +25C, VCC = 3.0 V) Parameter Rest current of overall IC in each mode Sleep mode Note Symbol Test Conditions MIN. TYP. MAX. Unit Rest status without input signal, including sampling clock. MS1 = L, MS2 = L Is Iw Ic Ia PD1 = L, PD2 = L PD1 = H, PD2 = L PD1 = H, PD2 = H PD1 = L, PD2 = H 1.3 10.5 18.0 22.1 2.2 13.0 22.0 26.0 3.5 15.5 25.3 30.0 mA mA mA mA Warm-up mode Calibration mode Active mode Rest current of PLL block in each clock mode Current when 1/100 divider is used Current when 256/3 divider is used Current when 1024/9 divider is used Current when 4096/65 divider is used Maximum mode control pin current 6 pin Current of PLL block. Overall current in calibration mode and active mode increases from that in basic mode (MS1 = L, MS2 = L). PD1 = H, PD2 = L. Iw1 MS1 = L, MS2 = L 5.3 6.5 7.6 mA Iw2 MS1 = L, MS2 = H 9.7 11.3 12.6 mA Iw3 MS1 = H, MS2 = L 10.2 12.1 13.5 mA Iw4 MS1 = H, MS2 = H 10.4 12.3 13.9 mA MS1 H application L application - -20 - -20 - -1 - -1 - - - - - - - - 20 - 20 - 1 - 1 - A A A A A A A A 12 pin MS2 H application L application 36 pin PD1 H application L application 37 pin PD2 H application L application fRFin = 1 575.42 MHz ICC1 GLNA NFLNA No Signals, 1-pin current PRFin = -40 dBm fRFin = 1 575 MHz 1.9 12.5 - -4.0 -25 -12 - - 2.3 15.0 3.0 -2.7 -21.8 -9.5 11.2 - j21.5 16.4 - j136.6 2.7 17.5 3.5 - - - - - mA dB dB dBm dBm dBm PO(SAT)LNA PRFin = -10 dBm PLNA-1 IIP3LNA ZinLNA fRFin = 1 575.42 MHz fRFin = 1 575.42 MHz, 1 576.42 MHz Calculated from S-parameter where input DC cut capacitance = 1 nF, output load L = 100 n, and DC cut capacitance = 1 nF Output Inpedance ZoutLNA Note Most of the current flows into the ADC ladder resistor (VDDana GNDana) in the sleep mode, and the sleep mode current between other VCC (VDD) and GND is 10 A maximum. 12 UPB1009K ELECTRICAL CHARACTERISTICS (TA = +25C, VCC = 3.0 V) Parameter fRF = 1 575.42 MHz, f1stLOin = 1 636.80 MHz, f1stIF = 61.38 MHz ICC2 CGRF No Signals, 40 pin current PRFMIXin = -40 dBm 2.0 14.0 - -4.0 -29.0 -19.0 - - - - 2.5 16.1 12.8 -0.8 -25.5 -17.2 -34.5 -54.7 50.1 - j22.3 57.3 + j2.6 3.0 19.0 16.0 - - - -30 -30 - - mA dB dB SSBNFRFMIX SSBNF = 10*log (2*DSBNF (Linear value) -1) MHz PO (SAT) RFMIX PRFMIXin = -10 dBm PRFMIX-1 IIP3RFMIX fRFMIXin = 1 575.42 MHz fRFMIXin = 1 575.42 MHz, 1 576.42 MHz f1stLO = 1 636.8 MHz Leakage of 1 636.8 MHz frequency when VCO oscillates correctly. Calculated from S-parameter where input DC cut capacitance = 1 nF and output DC cut capacitance = 1 nF Maximum IF Output Input 1dB Compression Level Input 3rd Order Intercept Point dBm dBm dBm LO Leakage to IF Pin LO Leakage to RF Pin Input Inpedance LOIF LORF ZinMIX dBm dBm Output Inpedance ZoutMIX f1stFin = 61.38 MHz, f2ndLOin = 65.472 MHz, ZL = 2 k ICC3 No Signals, 39 pin current 6.3 66.0 45.0 19.5 - 20.0 7.3 70.3 51.2 26.4 0.7 25.0 8.5 75.0 58.0 33.5 1.0 - - 17.5 - mA dB dB dB dB dB CG (GV) IF VAGC = 0.5 V VAGC = 1.5 V VAGC = 2.5 V In Band Gain Fluctuation Out Of Band Attenuation CG1 CG2 CGRange NFIF VO (SAT) IF PIF-1 3.092 to 5.092 MHz Gain difference at 4.092 MHz and 9.092 MHz, VAGC = 0.5 V VAGC = 0 to 2.5 V VAGC = 0.5 V (at maximum gain) Pin = -50 dBm, VAGC = 0.5 V f1stIFin = 61.38 MHz VAGC = 0.5 V VAGC = 1.5 V VAGC = 2.5 V Conversion Gain Range IF SSB Noise Figure Maximum 2ndIF Output Input 1dB Compression Level 32.5 - 1.0 -70.5 -53.5 -37.0 -56.0 -38.0 -27.0 - - 43.9 13.7 1.3 -64.4 -44.9 -30.6 -51.3 -30.7 -21.4 69.3 - j4.8 163 + j3.8 dB dB VPP dBm dBm dBm dBm dBm dBm - - - - - - - - Input 3rd Order Intercept Point IIP3IF f1stIFin1 = 61.28 MHz VAGC = 0.5 V f1stIFin2 = 61.38 MHz VAGC = 1.5 V f2ndLO = 65.472 MHz VAGC = 2.5 V Input Inpedance ZinIF Output Inpedance ZoutIF Calculated from S-parameter where input DC cut capacitance = 1 nF and output DC cut capacitance = 100 nF 13 UPB1009K ELECTRICAL CHARACTERISTICS (TA = +25C, VCC = 3.0 V) Parameter 10 kHz - -30 Remarks 1. Timing characteristics of ADC during normal operation A buffer amplifier is internally inserted before the ADC core of the PB1009K. The bias of this buffer amplifier is controlled by the signal input from the DC trim pin, and is used to eliminate the DC offset of the ADC. Because the ladder resistor of the ADC is directly connected between VDDana and GNDana, changes in VDDana affect the resolution of the ADC. 14 UPB1009K As illustrated in the operation timing chart below, the data of SampleN is pipeline delayed by 1.5 clocks during normal operation, and is output at the rising edge of the sample clock with output delay time Tod. When the operation is changed from normal operation to power-down operation, the status of the output data immediately before the power-down operation is retained (drive status). (a) Normal Operation SampleN+2 SampleN+3 SampleN 2ndIFin Tds SampleN+1 SampleN+4 SampleN+5 Tclk Tch Tcl SCKin Tpld Tds Toh D0-D3 N-2 N-1 N N+1 N+2 N+3 : Analog signal sampling timing The following table shows each timing parameter for reference purposes. Symbol Tod Tpld Tds Parameter Output Delay Pipeline Delay Sampling Delay (Aperture Delay) Output Hold Time Test Conditions CL = 10 pF, fclk = 19.2 MHz MIN. - - - 2 TYP. - 1.5 2 - MAX. 12 - - - Unit ns clock ns Toh ns 15 UPB1009K Remarks 2. Power-down timing characteristics of ADC The output code of the ADC of the PB1009K is undefined for 7.5 clocks after the power-down signal is cleared when the ADC returns from the power-down status to normal operation. (b) Power-down Operation PDB N 2ndIFin N+1 SCKin D0-D3 N undefined Note N+1 : Analog signal sampling timing Note The output data is undefined from the start of the power-down operation to the 7.5th clock from the falling edge of the clock at which the power-down operation is cleared. 16 UPB1009K TYPICAL CHARACTERISTICS (TA = +25C, VCC = 3.0 V, unless otherwise specified) IC TOTAL CHARACTERISTICS TOTAL CIRCUIT CURRENT vs. SUPPLY VOLTAGE 35 Total Circuit Current ICCTotal (mA) 30 25 20 15 10 5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 TA = +85C +25C -40C Supply Voltage VCC (V) Remark The graphs indicate nominal characteristics. 17 UPB1009K PRE-AMPLIFIER BLOCK CHARACTERISTICS OUTPUT POWER vs. INPUT POWER 0 -5 -10 -15 -20 -25 -30 -50 TA = +85C +25C -40C 20 10 PREAMP GAIN vs. FREQUENCY Output Power Pout (dBm) Power Gain GLNA (dB) 0 -10 -20 -30 TA = +85C +25C -40C -40 -30 -20 -10 0 -40 100 300 500 700 900 1 100 1 300 1 500 1 700 1 900 2 000 Frequency f (MHz) Input Power Pin (dBm) PREAMP NOISE FIGURE vs. FREQUENCY 5.0 4.5 0 -10 PREAMP IM CHARACTERISTICS Output Power Pout (dBm) Noise Figure NFLNA (dB) 4.0 3.5 3.0 2.5 2.0 1.5 TA = +85C +25C -40C -20 -30 -40 -50 -60 -70 -80 -45 -40 -35 -30 TA = +85C +25C -40C -25 -20 -15 -10 -5 1.0 1 545 1 555 1 565 1 575 1 585 1 595 1 605 1 615 Frequency f (MHz) Input Power Pin (dBm) Remark The graphs indicate nominal characteristics. 18 UPB1009K RF MIX BLOCK CHARACTERISTICS OUTPUT POWER vs. INPUT POWER 0 -5 -10 -15 -20 -25 -30 -45 0 -10 RF MIX IM CHARACTERISTICS Output Power Pout (dBm) Output Power Pout (dBm) -20 -30 -40 -50 -60 -70 TA = +85C +25C -40C -40 -35 -30 -25 -20 -15 -10 TA = +85C +25C -40C -35 -25 -15 -5 5 -80 -50 -45 Input Power Pin (dBm) Input Power Pin (dBm) RF CONVERSION GAIN vs. FREQUENCY CHARACTERISTICS 25 25 RF NOISE FIGURE vs. FREQUENCY CHARACTERISTICS RF Noise Fingure SSBNFRFMIX (dB) RF Conversion Gain CGRF (dB) 20 TA = +85C +25C 20 15 -40C 15 TA = +85C +25C -40C 10 10 5 30 40 50 60 70 80 90 5 30 40 50 60 70 80 90 Frequency f (MHz) Frequency f (MHz) Remark The graphs indicate nominal characteristics. 19 UPB1009K IF BLOCK CHARACTERISTICS OUTPUT POWER vs. INPUT POWER 15 10 5 0 -5 -10 -15 -85 TA = +85C +25C -40C -80 -75 -70 -65 -60 -55 -50 10 0 Output Power Pout (dBm) IF IM CHARACTERISTICS Output Power Pout (dBm) -10 -20 -30 -40 -50 -60 -75 -70 -65 -60 TA = +85C +25C -40C -55 -50 Input Power Pin (dBm) Input Power Pin (dBm) IF-SSB NOISE FIGURE vs. 2ndIF FREQUENCY 70 IF-SSB Noise Figure NFIF (dB) IF Conversion Voltage Gain CG (GV) IF (dB) IF CONVERSION VOLTAGE GAIN vs. 2ndIF FREQUENCY 80 70 60 50 40 30 20 10 0 0.5 2.5 TA = +85C +25C -40C 4.5 6.5 8.5 10.5 11.5 60 50 40 30 20 10 0 0 2 TA = +85C +25C -40C 4 6 8 10 12 2ndIF Frequency f (MHz) 2ndIF Frequency f (MHz) IF CONVERSION VOLTAGE GAIN vs. AGC VOLTAGE IF Conversion Voltage Gain CG (GV) IF (dB) 80 70 60 50 40 30 20 10 0 0 0.5 TA = +85C +25C -40C 1.0 1.5 2.0 2.5 3.0 3.5 AGC Voltage VAGC (V) Remark The graphs indicate nominal characteristics. 20 UPB1009K VCO MODULATION SENSITIVITY CHARACTERISTICS VCO CONTROL VOLTAGE vs. VCO FREQUENCY 3.0 VCO Control Voltage VT (V) 2.5 2.0 1.5 1.0 0.5 0 1 300 TA = +85C +25C -40C 1 400 1 500 1 600 1 700 1 800 1 900 VCO Frequency fVCO (MHz) C/N CHARACTERISTICS Ref = -10 dBm Atten 5 dB Mkr1 = 10.0 kHz Noise -81.78 dB/Hz Ref = -10 dBm Atten 5 dB Mkr1 = 10.0 kHz Noise -81.92 dB/Hz Center = 1.637 GHz Res BW 1 kHz VBW 1 kHz Span 100 kHz Sweep 300 ms (401 pts) Center = 1.637 GHz Res BW 1 kHz VBW 1 kHz Span 100 kHz Sweep 300 ms (401 pts) Ref = -10 dBm Atten 5 dB Mkr1 = 10.0 kHz Noise -81.23 dB/Hz Center = 1.637 GHz Res BW 1 kHz VBW 1 kHz Span 100 kHz Sweep 300 ms (401 pts) Remark The graphs indicate nominal characteristics. 21 UPB1009K SINAD CHARACTERISTICS OF A/D CONVERTOR (IFin = 5.17 MHz, SCLKin = 20.48 MHz) +10 0 -10 TA = +25C SNR = 25.4 dB SINAD = 25.3 dBc SFDR = 42.3 dB ENOB = 3.91 bit THD = -40.9 dBc +10 0 -10 TA = -40C SNR = 25.4 dB SINAD = 25.3 dBc SFDR = 41.1 dB ENOB = 3.91 bit THD = -40.4 dBc AMPLITUDE (dB) -20 -30 -40 -50 -60 -70 -80 0 2 4 6 AMPLITUDE (dB) -20 -30 -40 -50 -60 -70 8 10 12 -80 0 2 4 6 8 10 12 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) +10 0 -10 TA = +85C SNR = 25.4 dB SINAD = 25.3 dBc SFDR = 43.7 dB ENOB = 3.92 bit THD = -42.1 dBc AMPLITUDE (dB) -20 -30 -40 -50 -60 -70 -80 0 2 4 6 8 10 12 ANALOG INPUT FREQUENCY (MHz) Remark The graphs indicate nominal characteristics. 22 UPB1009K MEASUREMENT CIRCUIT 21 AGCout 20 AGCin 19 SCKin 18 D3 17 D2 16 D1 15 D0 100 k VCC 100 k 82 pF 100 nF 100 nF 33 VCC 32 31 30 29 28 27 26 25 24 23 22 34 100 nF 82 pF 35 22 PD1 23 PD2 24 1stIFin 1 nF - - + 4bit ADC + - 21 20 100 k 100 nF 100 k + DCOFFin 14 DCOFFout 13 36 37 38 39 Pwdctrl Logic VGC LPF IFamp 1/4 50 19 18 2ndIFin 12 100 nF 2ndIFout 11 100 nF 2 k 17 65/1024 VCC 100 nF 82 pF 9/256 40 1/25 16 1 nF CLKout 10 25 1stIFout VCC 100 nF 1 nF 41 42 82 pF 3/64 15 PLL PD Fref 14 82 pF 100 nF VCC 43 PreAmp 1 PreAmpin 1 nF 7 pF 3.9 nH 1stMIX OSC CP 13 12 10 11 100 pF 100 pF 1 nF 8.2 nF 1.5 k 10 k 10 k 100 nF REFin 9 1 nF 44 1 2 3 4 5 6 VCC VCC 3.9 nH 1 nF 100 nF 750 F 82 pF 22 k 1 nF 100 nF 1 nF MS2 8 7 8 9 1 nF 1 k PreAmpout 1stMIXin Presin MS1 2 3 4 5 6 CPout VCOc 7 23 UPB1009K DESCRIPTION OF PINS OF TEST CIRCUIT Pin No. 1 2 3 4 5 6 7 Pin Function Preamplifier Input Preamplifier Output RF Mixer Input MS1 Prescaler Input VCO Power Control Pin Pin Name PreAmpin PreAmpout 1stMIXin MS1 Presin VCOc Pin No. 14 15 16 17 18 19 20 Sampling Signal Input AGC Input Pin Function DC Offset Input Digital Signal Output Pin Pin Name DCOFFin D0 D1 D2 D3 SCKin AGCin VT Measurement Pin (Charge Pump CPout Output) MS2 Reference Clock Input Clock Output 2ndIF Output 2ndIF Input DC Offset Output MS2 REFin CLKout 2ndIFout 2ndIFin DCOFFout 8 9 10 11 12 13 21 22 23 24 25 AGC Control Voltage Output AGCout PD1 Output (Default onboard : GND) PD1 PD1 Output (Default on board : VCC) PD2 1stIF Input 1stIF Output 1stIFin 1stIFout 24 UPB1009K APPLICATION CIRCUIT AGCout SCLKout DCOFF D3 D2 D1 100 k VCC 100 nF 100 nF 82 pF 33 VCC 32 31 30 29 28 27 D0 26 25 24 23 100 k 34 100 nF 82 pF 22 - - 35 RFPD1 RFPD2 36 37 38 1 nF + + 4bit ADC + - 21 100 nF 20 19 Pwdctrl Logic VGC LPF IFamp 1/4 100 nF 18 17 39 IFSAW VCC 100 nF 82 pF 65/1024 9/256 40 16 1 nF CLKout 1/25 41 VCC 100 nF 1 nF 3/64 15 PLL PD Fref 14 82 pF 100 nF VCC 42 82 pF 43 PreAmp 44 7 pF 3.9 nH 1 nF VCC 4.7 nH 1stMIX OSC CP 13 12 10 11 REFin 1 nF MS2 1 2 3 4 5 6 7 8 82 pF 9 100 pF 22 k 100 nF 1 nF 8.2 nF 500 F VCC 1.5 k RFSAW 1 pF 510 VCC 5.6 nH 1 nF 100 nF out 3.9 nH 100 nF 100 nF 10 nF in AMP TopSAW PD1 0 1 1 0 PD2 0 0 1 1 RFin Power-down mode Sleep mode (full off) Warm-up mode (PLL on) Calibration mode (PLL on) Active mode (full on) MS1 0 0 1 1 MS1 MS2 0 1 0 1 TCXO 16.368/16.384 MHz 19.2 MHz 14.4 MHz 26.0 MHz N 100 256/3 1024/9 4096/65 25 UPB1009K PACKAGE DIMENSIONS 44-PIN PLASTIC QFN (UNIT: mm) 6.20.2 6.00.2 6.00.2 6.20.2 44 Pin 1 Pin 6.20.2 6.00.2 (Bottom View) 0.180.05 0.550.2 0.14+0.10 -0.05 6.20.2 6.00.2 1.0MAX. 0.4 Caution The island pins located on the corners are needed to fabricate products in our plant, but do not serve any other function. Consequently the island pins should not be soldered and should remain non-connection pins. 26 UPB1009K NOTES ON CORRECT USE (1) Observe precautions for handling because of electro-static sensitive devices. (2) Form a ground pattern as widely as possible to minimize ground impedance (to prevent abnormal oscillation). (3) Keep the wiring length of the ground pins as short as possible. (4) Connect a bypass capacitor to the VCC pin. (5) High-frequency signal I/O pins must be coupled with the external circuit using a coupling capacitor. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your nearby sales office. Soldering Method Infrared Reflow Soldering Conditions Peak temperature (package surface temperature) Time at peak temperature Time at temperature of 220C or higher Preheating time at 120 to 180C Maximum number of reflow processes Maximum chlorine content of rosin flux (% mass) Peak temperature (package surface temperature) Time at temperature of 200C or higher Preheating time at 120 to 150C Maximum number of reflow processes Maximum chlorine content of rosin flux (% mass) Peak temperature (molten solder temperature) Time at peak temperature Preheating temperature (package surface temperature) Maximum number of flow processes Maximum chlorine content of rosin flux (% mass) Peak temperature (pin temperature) Soldering time (per side of device) Maximum chlorine content of rosin flux (% mass) : 260C or below : 10 seconds or less : 60 seconds or less : 12030 seconds : 3 times : 0.2%(Wt.) or below : 215C or below : 25 to 40 seconds : 30 to 60 seconds : 3 times : 0.2%(Wt.) or below : 260C or below : 10 seconds or less : 120C or below : 1 time : 0.2%(Wt.) or below : 350C or below : 3 seconds or less : 0.2%(Wt.) or below Condition Symbol IR260 VPS VP215 Wave Soldering WS260 Partial Heating HS350 Caution Do not use different soldering methods together (except for partial heating). Life Support Applications These NEC products are not intended for use in life support devices, appliances, or systems where the malfunction of these products can reasonably be expected to result in personal injury. The customers of CEL using or selling these products for use in such applications do so at their own risk and agree to fully indemnify CEL for all damages resulting from such improper use or sale. 12/04/2003 A Business Partner of NEC Compound Semiconductor Devices, Ltd. 27 |
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